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ZL50130 Ethernet Pseudo-Wires across a PSN
Data Sheet Applications
* Ethernet Pseudo-Wires across a Packet Switch Network Ordering Information ZL50130 PBGA -40C to +85 C System Interfaces * * * Flexible 32-bit host CPU interface (Motorola PowerQUICCTM II compatible) Dual address DMA transfer of packets to or from the CPU On-chip packet memory for self-contained operation Flexible, multi-protocol packet encapsulation, with support for IPv4/6, MPLS, L2TP, PWE3 Wire speed processing and forwarding of packets Packet sequencing and re-ordering where required Four classes of service with programmable priority mechanisms (WFQ and SP) Flexible classification of incoming packets at layers 2, 3, 4 and 5
October 2004
Features
Ethernet Pseudo-Wire Emulation Functions Supports the following functions for Ethernet PseudoWire emulation over the packet domain: * * * * Transports the complete Ethernet frame (less preamble and FCS) across the PSN Supports up to 127 point-to-point pseudo-wire links across the PSN VLAN priority field may be used to determine class of service on the PSN complies with the standards for Ethernet pseudowires proposed in the IETF's PWE3 working group 3 x 100 Mbit/s MII interfaces
Packet Processing Functions * * * * *
Network Interfaces *
Host Processor Interface Motorola PowerQUICCTM II compatible
packet receive/classifier protocol engine task manager
MAC
MAC
packet transmit - add layer 2/3 headers memory management / on-chip packet memory
Optional Off-chip Packet Memory 0-8 MBytes SSRAM
Figure 1 - High Level Overview
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Packet Switched Network Interface 100 Mbit/s MII
Host Processor Interface with DMA support Customer End Services 100 Mbit/s MII
ZL50130
Description
Data Sheet
The ZL50130 is part of a range of highly functional bridging devices. It provides the capability to extend a Local Area Network based on Ethernet across a service provider's packet switched network. This allows a company with multiple sites to manage its network as though it was a single LAN. In conjunction with an Ethernet aggregation network, the ZL50130 provides the dataplane requirements of the interworking function between the customer end services and the provider's packet switched network (see Figure 2). It can support wire-speed processing of up to 100 Mbit/s of traffic in each direction, and provides up to 127 separate pseudo-wire connections across the PSN. Packets arriving from a single customer end service may all be directed onto a single pseudo-wire, or split across multiple connections based on source and destination addresses. This is useful in the case where the customer is using the Ethernet pseudo-wire service to connect multiple sites. On packet egress the device includes four different classes of service, allowing priority treatment of customer traffic, depending on the service level agreement between the customer and provider. The user priority field in the packet's VLAN tag (if any) may be used to determine the appropriate class of service to be used on the PSN. Packets received from the Ethernet interfaces are parsed to determine the egress destination, and are appropriately queued to the customer end service, passed up to the host processor, or sent back toward the packet interface. Again there are four different classes of service to allow differentiation between customers with different service level agreements, or based on the use of VLAN tag priority. The ZL50130 includes sufficient on-chip memory to allow completely self-contained operation, reducing system costs and simplifying the design. For applications that do require more memory (e.g., where the network has a very high packet delay variation), the device supports up to 8 Mbytes of external synchronous ZBT SRAM.
Provider Edge Interworking Function
Customer End Services Ethernet Switch
e.g. MVTX2604 MVTX2804 aggregation and adaptation functions
ZL50130 Ethernet Pseudo-Wire Device
Host Processor Interface with DMA support packet receive/classifier MAC protocol engine task manager MAC
Phy
Packet Switch Network
Phy Phy Phy Phy Phy Phy Phy Phy
- add layer 2/3 headers
packet transmit
memory management / on-chip packet memory
PSN bound flow CE bound flow
Figure 2 - Provider Edge Inter-working Function using the ZL50130
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ZL50130 Table of Contents
Data Sheet
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 PSN-Bound Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 CE-Bound Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.3 Host Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.4 External Memory Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.0 Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Task Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Packet Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Packet Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4.1 Packet Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.2 Classifier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 JTAG Interface and Board Level Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 Packet Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 System Function Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5 Test Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5.1 Administration and Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5.2 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6 Miscellaneous Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.7 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.8 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.0 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 JTAG Interface and Board Level Test Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2 External Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3 Miscellaneous Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.0 Memory Map and Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.0 Test Modes Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.1 System Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.2 System Tri-State Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.3 System Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 System Tri-state Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.0 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4 Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.5 Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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ZL50130 Table of Contents
Data Sheet
9.0 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 Packet Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1.3 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 External Memory Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.4 System Function Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.5 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.0 Power Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.0 Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 High Speed Clock & Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.1 External Memory Interface - special considerations during layout. . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.2 MAC Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.0 Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.1 External Standards/Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.2 Zarlink ZL50130 Product Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.0 Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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ZL50130 List of Figures
Data Sheet
Figure 1 - High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Provider Edge Inter-working Function using the ZL50130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 3 - ZL50130 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4 - ZL50130 Data Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5 - ZL50130 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6 - Task Manager Routing Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7 - MII Transmit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 8 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 9 - Management Interface Timing for Ethernet Port - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 10 - Management Interface Timing for Ethernet Port - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 11 - External RAM Read and Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 12 - CPU Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 13 - CPU Write - MPC8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 14 - CPU DMA Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 15 - CPU DMA Write - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 16 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 17 - JTAG Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 18 - Powering Up the ZL50130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 19 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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ZL50130 List of Tables
Data Sheet
Table 1 - DMA Maximum Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 2 - MII Management Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 3 - MII Port 0 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 4 - MII Port 1 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5 - MII Port 2 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6 - MII Port 3 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 7 - External Memory Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8 - CPU Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 9 - System Function Interface Package Ball Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 10 - Administration/Control Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 11 - JTAG Interface Package Ball Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 12 - Miscellaneous Inputs Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 13 - Power and Ground Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 14 - No Connection Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 15 - Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 16 - Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 17 - Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 18 - MII Transmit Timing - 100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 19 - MII Receive Timing - 100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 20 - MAC Management Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 21 - External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 22 - CPU Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 23 - System Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 24 - JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Zarlink Semiconductor Inc.
ZL50130
1.0 Changes Summary
Data Sheet
The following table captures the changes from the September 2004 issue. Page 10, 11 41 38 10 Item Figure 5 and Ball Signal Assignment Table 8.0 DC Characteristics Table and Output Levels Table Section 4.8 Figure 5 Change Corrected Mx_LINKUP_LED pin assigment. Added Electrical Characteristics to differentiate between 3.3 V and 5 V tolerant pins. Added Internal Connection (IC) table. Changed PULL_HI and PULL_LO pins to ICC_VDD_IO and IC_GND.
2.0
2.1
Introduction
Overview
The ZL50130 provides the data-plane processing to enable layer 2 Ethernet service to be extended over a packet switched network, such as an IP or MPLS system. The device encapsulates the Ethernet frames into IP or MPLS packets, and forwards them into the packet network for re-construction at the far end. This has a number of applications, including layer 2 VPNs (Virtual Private Networks).
Transparent data flow between customer LANs (layer 2 VPN service)
ZL50130
Ethernet Service
Ethernet Pseudo-Wire device
interworking function Service provider's packet switched network
ZL50130
Ethernet Pseudo-Wire device
interworking function Ethernet Service
Customer LAN
Customer LAN
Figure 3 - ZL50130 Operation The ZL50130 is capable of wire speed processing and forwarding of packets, and includes support for the "Martini-style" layer 2 pseudo-wire protocols currently in development by the IETF's PWE3 (Pseudo-Wire Edge-to-Edge Emulation) working group (draft-ietf-pwe3-ethernet-encap).
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Zarlink Semiconductor Inc.
ZL50130
2.2 Basic Operation
Data Sheet
A diagram of the ZL50130 device is given in Figure 4, which shows the major data flows between functional components.
Provider Edge Interworking Function
Customer End Services Ethernet Switch
e.g. MVTX2604 MVTX2804 aggregation and adaptation functions
ZL50130 Ethernet Pseudo-Wire Device
Host Processor Interface with DMA support packet receive/classifier MAC protocol engine task manager MAC
Phy
Packet Switch Network
Phy Phy Phy Phy Phy Phy Phy Phy
- add layer 2/3 headers
packet transmit
memory management / on-chip packet memory
PSN bound flow CE bound flow
Figure 4 - ZL50130 Data Flows
2.2.1
PSN-Bound Flow
The Ethernet switch device aggregates Ethernet frames received from each customer into a single Ethernet connection. Packets are forwarded on this connection to the ZL50130, and received by its customer-facing MAC interface. Valid packets are passed to the Packet Classifier to determine the destination. The Protocol Engine handles the data-plane requirements of the main higher level protocols (layers 4 and 5) used in typical applications of the ZL50130. These include the Ethernet pseudo-wire control word (basically a 16-bit sequence number), L2TPv3 connection ID, L2TP version 2 and UDP. The Protocol Engine can add a header to the datagram containing up to 24 bytes. This header is largely static information, and is programmed directly to the CPU. The header may contain a number of dynamic fields, including a length field, checksum, sequence number and a timestamp. The location, and in some cases, the length of these fields is also programmable, allowing the various protocols to be placed at variable locations within the header. Packets ready for transmission are queued to the switch fabric interface by the Packet Transmit block. Four classes of service are provided, allowing some packet streams to be prioritized over others. On transmission, the Packet Transmit block appends a programmable header, which has been set up in advance by the control processor. Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet IP, or the MPLS tunnel and the VC labels. Finally, packets are sent out to the packet switched network by the PSN-facing MAC.
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Zarlink Semiconductor Inc.
ZL50130
2.2.2 CE-Bound Flow
Data Sheet
The flow in the reverse direction is essentially similar to the PSN-bound flow. Packets from the PSN are received by its PSN-facing MAC interface. Valid packets are passed to the Packet Classifier to determine the destination. Once this has been determined, the packets are passed to the Packet Transmit block for forwarding onto the customer. This time, the Packet Transmit block strips the tunnel header appended on original transmission into the PSN. The packets are then queued for transmission by the customer-facing MAC.
2.2.3
Host Packet Generation
The control processor can generate packets directly, allowing it to use the network for out-of-band communications. This can be used for out-of-band transmission of control data or network setup information, e.g., routing information. The host interface can also be used by a local resource for network transmission of processed data. The device supports DMA transfers of packets to and from the CPU memory, using the host's own DMA controller.
2.2.4
External Memory Requirement
The ZL50130 includes a large amount of on-chip memory, such that for most applications, external memory will not be required. However, for some applications there may be a requirement for external memory. Therefore, the device allows the external connection of up to 8 Mbytes of synchronous ZBT SRAM.
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Zarlink Semiconductor Inc.
ZL50130
ZL50130 Package view from TOP side. Note that ball A1 is non-chamfered corner. 12 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
GND N/C N/C N/C
Data Sheet
3456
N/C N/C N/C N/C N/C N/C N/C N/C
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_D RAM_D ATA[3] ATA[1]
N/C
RAM_D ATA[0]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_D RAM_D RAM_D RAM_D RAM_D ATA[10] ATA[9] ATA[5] ATA[4] ATA[2] RAM_D RAM_D RAM_D RAM_D RAM_D ATA[15] ATA[13] ATA[12] ATA[6] ATA[7]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
GND
VDD_C ORE
N/C
N/C
N/C
N/C
VDD_C ORE
N/C
N/C
VDD_C ORE
N/C
N/C
N/C
N/C
VDD_C ORE
GND
N/C
N/C
N/C
N/C
M1_LIN KUP_LE M_MDIO
RAM_D RAM_D RAM_D RAM_D RAM_D RAM_D ATA[21] ATA[18] ATA[16] ATA[14] ATA[11] ATA[8] RAM_D RAM_D RAM_D RAM_D RAM_D VDD_C ATA[25] ATA[24] ATA[23] ATA[19] ATA[17] ORE RAM_D RAM_D RAM_D RAM_D RAM_D RAM_D ATA[29] ATA[28] ATA[27] ATA[26] ATA[22] ATA[20] RAM_PARAM_PA RAM_D RAM_D RITY[1] RITY[0] ATA[31] ATA[30] GND VDD_C ORE VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
N/C
N/C N/C
M2_LIN M3_LIN KUP_LE KUP_LE
N/C
VDD_C ORE
M_MDC M3_CRSM3_TXC M3_RXE LK R
M3_RXDM3_RXDM3_RXDM3_RXDM3_RXD M3_COL V [3] [2] [1] [0] VDD_C ORE GND M3_TXD M3_TXE M3_TXE M3_RXC [3] N R LK
VDD_IO
VDD_IO
RAM_PARAM_PARAM_PARAM_PARAM_PARAM_PA RITY[7] RITY[6] RITY[5] RITY[4] RITY[3] RITY[2] RAM_A RAM_A RAM_A RAM_A RAM_A RAM_A DDR[5] DDR[4] DDR[2] DDR[3] DDR[0] DDR[1] GND RAM_A RAM_A RAM_A DDR[6] DDR[7] DDR[8] GND VDD_C ORE GND
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_RXE M1_TXC M1_CRSM3_TXD M3_TXD M3_TXD R LK [0] [1] [2] VDD_C M1_REF M1_RXC ORE CLK LK N/C GND N/C N/C M1_RXD V
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_TXE M1_RXDM1_RXD GND R [2] [3] M1_TXE GND N N/C N/C N/C N/C
RAM_A RAM_A RAM_A RAM_A RAM_A DDR[9] DDR[10] DDR[11] DDR[13] DDR[16] RAM_A RAM_A RAM_A DDR[15] RAM_A IC_GND DDR[12] DDR[14] DDR[19] RAM_A RAM_A RAM_B IC_GND DDR[17] DDR[18] W_B N/C GND
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_TXD [2]
N/C
IC
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
M1_TXD M1_TXD [0] [3] VDD_C M1_TXD ORE [1] N/C M0_RXD [2]
M1_COLM1_RXD [1] N/C M1_RXD [0] N/C
A1VDD
VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO
N/C
GND
RAM_B RAM_B RAM_R SYSTE SYSTE W_A W_C W M_DEB M_CLK RAM_B RAM_B SYSTE GPIO[2] VDD_C W_D W_F M_RST ORE
VDD_IO
VDD_IO
N/C
M0_TXC M0_CRS LK N/C
N/C
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
N/C
M0_TXE M0_TXE R N N/C N/C
M0_RXD M0_RXE V R N/C M0_RXD [3]
RAM_B RAM_B GPIO[0] GPIO[3] GPIO[9] RAM_D W_E W_G ATA[33] RAM_B GPIO[4] GPIO[6] GPIO[10 RAM_D VDD_C W_H ] ATA[32] ORE GPIO[1] GPIO[7] GPIO[8] GPIO[15 RAM_D ] ATA[39] GND
M0_TXD [2]
N/C
VDD_C M0_TXD ORE [1]
N/C
N/C
M0_COLM0_RXD [1] N/C M0_RXD [0]
RAM_D RAM_D VDD_C JTAG_T CPU_ADCPU_AD VDD_C VDD_C CPU_DACPU_DACPU_DA VDD_C M2_RXCM2_RXD GND M0_TXD M0_TXD M0_REF ATA[45] ATA[52] ORE MS DR[2] DR[12] ORE ORE TA[8] TA[15] TA[23] ORE LK V [0] [3] CLK
GPIO[5] GPIO[11 GPIO[14 RAM_D RAM_D RAM_D RAM_D RAM_D TEST_M GND CPU_ADCPU_ADCPU_AD CPU_TACPU_DACPU_DACPU_DACPU_DACPU_DA M2_TXE M2_RXDM0_RXC M0_LIN M2_ACT M1_ACT M3_ACT ] ] ATA[38] ATA[43] ATA[44] ATA[51] ATA[60] ODE[1] DR[6] DR[14] DR[23] TA[1] TA[7] TA[12] TA[22] TA[30] R [1] LK KUP_LE IVE_LE IVE_LE IVE_LE GPIO[12 GPIO[13 RAM_D RAM_D RAM_D RAM_D RAM_D TEST_M JTAG_T CPU_ADCPU_ADCPU_ADCPU_AD CPU_CL CPU_D ] ] ATA[37] ATA[42] ATA[46] ATA[49] ATA[59] ODE[0] DO DR[4] DR[9] DR[16] DR[22] K REQ0 IC CPU_DACPU_DACPU_DACPU_DA M2_TXD M2_TXE M2_RXD M2_RXEM2_CRSM0_ACT TA[10] TA[16] TA[21] TA[27] [1] N [2] R IVE_LE
RAM_D RAM_D RAM_D RAM_D RAM_D RAM_D RAM_D JTAG_T IC_GND CPU_ADCPU_ADCPU_ADCPU_AD CPU_W CPU_SD CPU_IR CPU_DACPU_DACPU_DACPU_DACPU_DACPU_DA M2_TXD M2_RXDM2_RXD M2_TXC ATA[34] ATA[36] ATA[41] ATA[47] ATA[53] ATA[58] ATA[63] CK DR[7] DR[11] DR[17] DR[21] E ACK2 EQ1 TA[3] TA[6] TA[14] TA[20] TA[24] TA[29] [2] [0] [3] LK RAM_D RAM_D RAM_D RAM_D RAM_D RAM_D JTAG_T IC_GND CPU_ADCPU_ADCPU_ADCPU_ADCPU_AD CPU_O CPU_TS CPU_D ATA[35] ATA[40] ATA[48] ATA[54] ATA[57] ATA[62] RST DR[3] DR[8] DR[13] DR[18] DR[20] E _ALE REQ1 GND IC CPU_DACPU_DACPU_DACPU_DACPU_DACPU_DA M2_TXD M2_TXD M2_COL TA[4] TA[9] TA[13] TA[18] TA[25] TA[28] [0] [3]
RAM_D RAM_D RAM_D RAM_D TEST_M JTAG_T IC_GND CPU_ADCPU_ADCPU_ADCPU_AD GND CPU_CSCPU_SD IC_VDD CPU_IR CPU_DACPU_DACPU_DACPU_DACPU_DACPU_DACPU_DACPU_DA GND ATA[50] ATA[55] ATA[56] ATA[61] ODE[2] DI DR[5] DR[10] DR[15] DR[19] ACK1 _IO EQ0 TA[0] TA[5] TA[2] TA[11] TA[17] TA[19] TA[26] TA[31]
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
12
3456
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 5 - ZL50130 Package View and Ball Positions
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Zarlink Semiconductor Inc.
ZL50130
Ball Signal Assignment Ball Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 Signal Name GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C Ball Number B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 Signal Name N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C Ball Number C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23
Data Sheet
Signal Name N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C RAM_DATA[3] RAM_DATA[1] N/C RAM_DATA[0] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
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Zarlink Semiconductor Inc.
ZL50130
Ball Number D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 Signal Name N/C N/C N/C RAM_DATA[10] RAM_DATA[9] RAM_DATA[5] RAM_DATA[4] RAM_DATA[2] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C RAM_DATA[15] RAM_DATA[13] RAM_DATA[12] RAM_DATA[6] RAM_DATA[7] Ball Number F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G21 G22 G23 G24 G25 G26 H1 Signal Name GND VDD_CORE N/C N/C N/C N/C VDD_CORE N/C N/C VDD_CORE N/C N/C N/C N/C VDD_CORE GND N/C N/C N/C N/C M1_LINKUP_LED RAM_DATA[21] RAM_DATA[18] RAM_DATA[16] RAM_DATA[14] RAM_DATA[11] RAM_DATA[8] N/C N/C M2_LINKUP_LED M3_LINKUP_LED N/C M_MDIO RAM_DATA[25] Ball Number H2 H3 H4 H5 H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J21 J22 J23 J24 J25 J26 K1
Data Sheet
Signal Name RAM_DATA[24] RAM_DATA[23] RAM_DATA[19] RAM_DATA[17] VDD_CORE VDD_CORE N/C M_MDC M3_CRS M3_TXCLK M3_RXER RAM_DATA[29] RAM_DATA[28] RAM_DATA[27] RAM_DATA[26] RAM_DATA[22] RAM_DATA[20] VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO M3_RXDV M3_RXD[3] M3_RXD[2] M3_RXD[1] M3_RXD[0] M3_COL RAM_PARITY[1]
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Zarlink Semiconductor Inc.
ZL50130
Ball Number K2 K3 K4 K5 K6 K9 K18 K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L9 L11 L12 L13 L14 L15 L16 L18 L21 L22 L23 L24 L25 L26 M1 Signal Name RAM_PARITY[0] RAM_DATA[31] RAM_DATA[30] GND VDD_CORE VDD_IO VDD_IO VDD_CORE GND M3_TXD[3] M3_TXEN M3_TXER M3_RXCLK RAM_PARITY[7] RAM_PARITY[6] RAM_PARITY[5] RAM_PARITY[4] RAM_PARITY[3] RAM_PARITY[2] VDD_IO GND GND GND GND GND GND VDD_IO M1_RXER M1_TXCLK M1_CRS M3_TXD[0] M3_TXD[1] M3_TXD[2] RAM_ADDR[5] Ball Number M2 M3 M4 M5 M6 M9 M11 M12 M13 M14 M15 M16 M18 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N9 N11 N12 N13 N14 N15 N16 N18 N21 Signal Name RAM_ADDR[4] RAM_ADDR[2] RAM_ADDR[3] RAM_ADDR[0] RAM_ADDR[1] VDD_IO GND GND GND GND GND GND VDD_IO VDD_CORE M1_REFCLK M1_RXCLK N/C N/C M1_RXDV GND RAM_ADDR[6] RAM_ADDR[7] RAM_ADDR[8] GND VDD_CORE VDD_IO GND GND GND GND GND GND VDD_IO N/C Ball Number N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P9 P11 P12 P13 P14 P15 P16 P18 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R9 R11 R12
Data Sheet
Signal Name GND M1_TXER M1_RXD[2] M1_RXD[3] GND RAM_ADDR[9] RAM_ADDR[10] RAM_ADDR[11] RAM_ADDR[13] RAM_ADDR[16] GND VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[2] N/C M1_TXEN GND N/C N/C RAM_ADDR[12] RAM_ADDR[14] RAM_ADDR[15] RAM_ADDR[19] IC_GND IC VDD_IO GND GND
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Zarlink Semiconductor Inc.
ZL50130
Ball Number R13 R14 R15 R16 R18 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T9 T11 T12 T13 T14 T15 T16 T18 T21 T22 T23 T24 T25 T26 U1 U2 U3 Signal Name GND GND GND GND VDD_IO M1_TXD[0] M1_TXD[3] N/C N/C M1_COL M1_RXD[1] RAM_ADDR[17] RAM_ADDR[18] RAM_BW_B IC_GND GND A1VDD VDD_IO GND GND GND GND GND GND VDD_IO VDD_CORE M1_TXD[1] N/C GND N/C M1_RXD[0] N/C RAM_BW_A RAM_BW_C Ball Number U4 U5 U6 U9 U18 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V21 V22 V23 V24 V25 V26 W1 Signal Name RAM_RW SYSTEM_DEBUG SYSTEM_CLK VDD_IO VDD_IO N/C M0_RXD[2] N/C M0_TXCLK M0_CRS N/C N/C RAM_BW_D RAM_BW_F SYSTEM_RST GPIO[2] VDD_CORE VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO N/C M0_TXER M0_TXEN N/C M0_RXDV M0_RXER RAM_BW_E Ball Number W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11
Data Sheet
Signal Name RAM_BW_G GPIO[0] GPIO[3] GPIO[9] RAM_DATA[33] M0_TXD[2] N/C N/C N/C N/C M0_RXD[3] RAM_BW_H GPIO[4] GPIO[6] GPIO[10] RAM_DATA[32] VDD_CORE VDD_CORE M0_TXD[1] N/C N/C M0_COL M0_RXD[1] GPIO[1] GPIO[7] GPIO[8] GPIO[15] RAM_DATA[39] GND RAM_DATA[45] RAM_DATA[52] VDD_CORE JTAG_TMS CPU_ADDR[2]
14
Zarlink Semiconductor Inc.
ZL50130
Ball Number AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 Signal Name CPU_ADDR[12] VDD_CORE VDD_CORE CPU_DATA[8] CPU_DATA[15] CPU_DATA[23] VDD_CORE M2_RXCLK M2_RXDV GND M0_TXD[0] M0_TXD[3] M0_REFCLK N/C M0_RXD[0] GPIO[5] GPIO[11] GPIO[14] RAM_DATA[38] RAM_DATA[43] RAM_DATA[44] RAM_DATA[51] RAM_DATA[60] TEST_MODE[1] GND CPU_ADDR[6] CPU_ADDR[14] CPU_ADDR[23] CPU_TA CPU_DATA[1] CPU_DATA[7] CPU_DATA[12] CPU_DATA[22] CPU_DATA[30] Ball Number AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 Signal Name M2_TXER M2_RXD[1] M0_RXCLK M0_LINKUP_LED M2_ACTIVE_LED M1_ACTIVE_LED M3_ACTIVE_LED GPIO[12] GPIO[13] RAM_DATA[37] RAM_DATA[42] RAM_DATA[46] RAM_DATA[49] RAM_DATA[59] TEST_MODE[0] JTAG_TDO CPU_ADDR[4] CPU_ADDR[9] CPU_ADDR[16] CPU_ADDR[22] CPU_CLK CPU_DREQ0 IC CPU_DATA[10] CPU_DATA[16] CPU_DATA[21] CPU_DATA[27] M2_TXD[1] M2_TXEN M2_RXD[2] M2_RXER M2_CRS M0_ACTIVE_LED RAM_DATA[34] Ball Number AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9
Data Sheet
Signal Name RAM_DATA[36] RAM_DATA[41] RAM_DATA[47] RAM_DATA[53] RAM_DATA[58] RAM_DATA[63] JTAG_TCK IC_GND CPU_ADDR[7] CPU_ADDR[11] CPU_ADDR[17] CPU_ADDR[21] CPU_WE CPU_SDACK2 CPU_IREQ1 CPU_DATA[3] CPU_DATA[6] CPU_DATA[14] CPU_DATA[20] CPU_DATA[24] CPU_DATA[29] M2_TXD[2] M2_RXD[0] M2_RXD[3] M2_TXCLK RAM_DATA[35] RAM_DATA[40] RAM_DATA[48] RAM_DATA[54] RAM_DATA[57] RAM_DATA[62] JTAG_TRST N/C CPU_ADDR[3]
15
Zarlink Semiconductor Inc.
ZL50130
Ball Number AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 Signal Name CPU_ADDR[8] CPU_ADDR[13] CPU_ADDR[18] CPU_ADDR[20] CPU_OE CPU_TS_ALE CPU_DREQ1 IC CPU_DATA[4] CPU_DATA[9] CPU_DATA[13] CPU_DATA[18] CPU_DATA[25] CPU_DATA[28] M2_TXD[0] M2_TXD[3] M2_COL GND RAM_DATA[50] RAM_DATA[55] RAM_DATA[56] RAM_DATA[61] TEST_MODE[2] JTAG_TDI IC_GND CPU_ADDR[5] CPU_ADDR[10] CPU_ADDR[15] CPU_ADDR[19] GND CPU_CS CPU_SDACK1 IC_VDD_IO CPU_IREQ0 Ball Number AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal Name CPU_DATA[0] CPU_DATA[5] CPU_DATA[2] CPU_DATA[11] CPU_DATA[17] CPU_DATA[19] CPU_DATA[26] CPU_DATA[31] GND
Data Sheet
N/C - No Connect Pins, these unused pins must be left open circuit. IC - Internally Connected. Must be left open circuit. IC_GND - Internally Connected. Tie to ground. IC_VDD_IO - Internally Connected. Tie to VDD_IO.
16
Zarlink Semiconductor Inc.
ZL50130
3.0
3.1
Data Sheet
Functional Block Descriptions
Task Manager
Conceptually, the task manager performs the function of a router in the centre of the chip, directing packets to the appropriate processing blocks. The architecture is based on the task-oriented approach derived from computer science, in which each functional block is considered a service provider or "subroutine". As a packet is processed in the chip, it receives a specific service from a block, returns the flow of control to the task manager and is then forwarded to the next block for service. The process is carried on until it reaches the egress port, as shown in Figure 6. The solid arrows illustrate the actual flow of control, while the dotted lines represent the equivalent point-to-point path.
Task Manager
Task Block 1
Task Block 2
Task Block 3
Task Block 4
Figure 6 - Task Manager Routing Concept The main function of the task manager is to dispatch task messages to the task blocks. Each task block interfaces only with the task manager, not with other task blocks. The task messages passed between blocks contain pointers to the relevant data, instructions as to what to do with the data and ancillary information about the packet. Effectively this means the flow of data through the device can be programmed by setting the task message contents appropriately. Features include: * * * Flexible routing of packets through the device Common interface to all functional blocks Communication of key parameters between blocks
3.2
Protocol Engine
The Protocol Engine handles the data-plane requirements of the upper level protocols at layers 4 and 5. It has been designed to handle the requirements of the specific protocols expected to be used in typical applications: UDP, L2TP versions 2 and 3, and Ethernet pseudo-wire. However, it is not exclusively limited to these protocols, since it works by providing a number of dynamic fields that can be updated as required. Therefore other protocol headers containing the same types of dynamic fields can also be constructed. The Protocol Engine can add a header to the datagram containing up to 24 bytes. This header is largely static information and is programmed directly by the CPU. This header may contain a number of dynamic fields, including a length field, checksum, sequence number and a timestamp. The location, and in some cases the length of these fields is also programmable, allowing the various protocols to be placed at variable locations within the header.
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Zarlink Semiconductor Inc.
ZL50130
Features include: * * Up to 24 bytes of higher layer protocol headers (layers 2 to 5) Specific support for the following protocols: * * * * * * * UDP (RFC 768) L2TP versions 2 and 3 (RFC 2661, draft-ietf-l2tpext-l2tp-base-02) Ethernet PW (draft-ietf-pwe3-ethernet-encap) 16 bit checksum over header and data 16 bit datagram length field 8 and 16 bit sequence numbers
Data Sheet
Support for the following dynamic fields:
3.3
Packet Transmit
The Packet Transmit block serves two main functions. Firstly, it directs the packets to the appropriate Ethernet MAC. Four separate queues are directed at each MAC, allowing different classes of service to be established. For instance, packets from the host can be given lower priority service than normal transmission packets. The queues can be managed either on a strict priority basis, or using Weighted Fair Queuing (WFQ). There is also a limit on the maximum number of packets in an individual queue. Beyond the limit packets are dropped, avoiding a large build-up in packet delay variation, and preventing the memory becoming full and thereby "crashing" the device. Secondly, the Packet Transmit block adds a header to the packet before it is sent out for transmission. Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet, IP and MPLS. While the main contents of this header are static and programmed by the user in a block of memory reserved for each context, certain fields can be dynamically adjusted by the block. These are the Ethernet, IPv4 and IPv6 length fields and the IPv4 identification field (effectively a sequence number). Once the packet header has been appended, any packets that are still smaller than the minimum Ethernet packet size (64 bytes) are padded. Features include: * * Four separate queues to each Ethernet MAC, with different classes of service Queue disciplines on packet interface are: * * * * * * * Weighted Fair Queuing with programmable weights Strict Priority
Programmable drop threshold when queues get too big Adds up to 64 bytes of layer 2 and layer 3 headers Automatically adjusts Ethernet length, IP length and IP identification fields Pads small packets to meet the 64 byte minimum Ethernet packet size Packets can be directed to any of the four Ethernet MACs
3.4
Packet Receive
The Packet Receive block handles two main functions: writing the packet into memory, and identifying the packet received. Packets are written into memory as they arrive at the device. A small buffer is used to cope with simultaneous requests for memory access. The device is capable of accepting packets on 3 ports in MII mode, either ports 0, 1 and 2, or ports 0, 1 and 3.
18
Zarlink Semiconductor Inc.
ZL50130
3.4.1 Packet Classification
Data Sheet
The ZL50130 contains an extremely flexible packet classifier, capable of operating on layers 2 to 5, and identifying 272 separate flows. For instance, it can identify a separate data and control flow for each context, and a number of other separate flows for sending to the CPU. In addition, the classifier can quickly identify certain specific types of control traffic intended for the CPU, such as ARP, RARP and multicast messages. The classifier is designed to handle all the protocols likely to occur in networks using the standards developed by the IETF's PWE3, either alone or in combination. These include Ethernet (with VLAN and SNAP), IPv4, IPv6, MPLS, UDP, L2TP versions 2 and 3, and the Ethernet pseudo-wire control word. Typical protocol stacks which are expected to be used and can be handled by the ZL50130 include (but are not limited to) the following:
Ethernet IPv4 / IPv6 L2TPv3 Ethernet IPv4 / IPv6 UDP L2TPv2 Ethernet PW Ethernet PW Ethernet PW Ethernet PW Ethernet MPLS (tunnel label) MPLS (VC label) Ethernet Stacked VLAN (tunnel tag) Stacked VLAN (VC tag)
The classifier is also used to detect traffic directed to the host CPU. Features include: * Automatic forwarding of the following control traffic types to the CPU: * * * * * * * * * * * * * 802.1 control packets Ethernet broadcast packets IP multicast packets ARP packets RARP packets
Four separate traffic classes Traffic class identified on any combination fields within the first 64 bytes 272 traffic flows (e.g., 128 data, 128 control, 16 host traffic and loopback) Flow identification based on up to 96 bits, extracted from any field in the first 96 bytes Mis-connection check, based on up to 64 bits, extracted from any field in the first 96 bytes Host traffic can be directed to its queue IPv4 checksum verification Support for IP and UDP MIBS in combination with the CPU
3.4.2
Classifier Operation
The classifier works in four steps. Firstly, the classifier checks the packet header to see if it is one of a number of fixed traffic types. These include 802.1 control packets, Ethernet broadcast packets, IP multicast packets, ARP and RARP packets. These types of packets are automatically forwarded to the CPU at high priority. Next the traffic is sorted into one of four pre-determined traffic classes. This is done by a comparison across the first 64 bytes of the packet. This will generally check fields such as Ethertype and the IP protocol field. In addition, the Ethernet and IP destination address fields can be checked, to ensure that the packet is intended for this device.
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Zarlink Semiconductor Inc.
ZL50130
Data Sheet
Once the class has been determined, a template is applied, extracting up to 96 bits from any field in the first 96 bytes. These are used to determine the individual flow. For example, this could be used to check the cookie value in the L2TPv3 header. The checksum fields can also be verified now, since the protocol stack in use has been determined. When the flow has been identified, up to 64 further bits may be compared to a pre-programmed value as a mis-connection check. For example, the SSRC field in the RTP header could be checked, or the cookie value in the L2TPv3 header. It could also be used to check Ethernet or IP source addresses, to check the packet came from the expected source. These 64 bits may again be extracted from any field in the first 96 bytes. The use of the mis-connection check helps to protect against denial of service attacks, since the cookie or SSRC values are usually hard to guess. At any stage, a failure to match results in the packet being directed to the CPU queue. This enables the host to view the packet and take appropriate action.
3.5
Ethernet MAC
The ZL50130 device contains four separate, IEEE standard 802.3 compliant, 100 Mbit/s Ethernet MACs. Each MAC is connected to a Physical Layer (PHY) device via a Media Independent Interface (MII). The MAC is responsible for data encapsulation/decapsulation. This includes frame alignment and synchronization, and detection of physical medium transmission errors. The MAC is capable of both full and half-duplex operation. In half-duplex mode it manages the collision avoidance and contention resolution process. In the event of a collision, the MAC will back off and attempt to re-send the packet up to 16 times. Packets for transmission are forwarded to the MAC by the Packet Formatter block. The MAC appends the frame check sequence, and generates the preamble and start of frame delimiter before transmitting out of the MII port. During packet reception, the MAC receive section verifies that the frame check sequence is correct, and that the packet is a valid length. Packets with an invalid frame check sequence, and data packets longer than a pre-programmed threshold and shorter than 64 bytes are dropped. For Ethernet pseudo-wire operation, the thresholds on the customer-facing MACs are usually set shorter than on the PSN-facing MAC. This is to avoid creating over-sized packets when the additional tunnel headers are added to the packet. The MAC also checks the destination field to determine if the packet is intended for the device. If the packet is accepted, it is forwarded on for packet classification, and to be entered into the appropriate destination queue. Illegal packets, or packets intended for a different destination are discarded. The MAC also collects statistics on the different types of packets transmitted and received on the Ethernet. The statistics collected are sufficient to enable the CPU to support the Interfaces sections of some common MIBs. Features include: * * * * * * * IEEE 802.3 compliant operation at 100 Mbit/s Industry-standard MII interface to the physical layer devices Full and half-duplex operation Generates preamble, start-of-frame delimiter and frame check sequence Collision avoidance and contention resolution in half-duplex mode Verifies frame check sequence and frame length, discarding frames that contain errors Statistics collection for common MIB support: * * RFC 1213 MIB II RFC 1757 Remote Network Monitoring MIB (for SMIv1)
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Zarlink Semiconductor Inc.
ZL50130
* * RFC 2819 Remote Network Monitoring MIB (for SMIv2) RFC 2863 Interfaces Group MIB
Data Sheet
3.6
Memory Management Unit
The Memory Management Unit handles all access to the on- and off-chip packet memory, arbitrating between the different modules requiring access. Efficient use of memory is maintained by allocating memory in small blocks or "granules". The ZL50130 includes a large amount of on-chip memory, such that for most applications, external memory will not be required. However, for some applications there may be a requirement for external memory. Therefore the device allows the connection of up to 8 Mbytes of synchronous ZBT SRAM. Features include: * * * * * * On-chip packet memory for self-contained operation Up to 8 Mbytes of off-chip packet memory Interfaces to bandwidth efficient ZBT SRAM devices Operates at 100 MHz 64 bit wide data path Supports one memory bank consisting of up to 2x32 bit devices or 1x64 bit device
3.7
Host Interface
The Host Interface is directly compatible with the Motorola PowerQUICCTM II microprocessor family. It provides the host CPU with read and write access to registers, internal memory blocks, and the main on- and off-chip data memory. The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own DMA controller. Features include: * * * * * Interfaces directly to PowerQUICCTM II (MPC8260) microprocessors using the GPCM 32 bit wide data bus Allows target access to all on-chip registers and memory, and to external packet memory DMA support, for transfer of packets to and from the host CPU Flexible interrupt controller
21
Zarlink Semiconductor Inc.
ZL50130
Table illustrates the maximum bandwidths achievable by an external DMA master. DMA Path ZL50130 to CPU only ZL50130 to CPU only CPU to ZL50130 only CPU to ZL50130 only Combined2 Combined
Note 1: Note 2: 2
Data Sheet
Packet Size >1000 bytes 60 bytes >1000 bytes 60 bytes >1000 bytes 60 bytes
Max Bandwidth Mbps1 50 6.7 60 43 58 (29 each way) 11 (5.5 each way)
Table 1 - DMA Maximum Bandwidths
Maximum bandwidths are the maximum the ZL50130 devices can transfer under host control, and assumes only minimal packet processing by the host. Combined figures assume the same amount of data is to be transferred each way.
3.8
JTAG Interface and Board Level Test Features
The JTAG interface is used to access the boundary scan logic for board level production testing.
4.0
External Interface Description
The following key applies to all tables: I Input O Output D Internal 100 k pull-down resistor present U Internal 100 k pull-up resistor present T Tristate Output
4.1
Packet Interfaces
The ZL50130 the packet interface is capable of 3 MII interfaces. Data for packet switching is based on Specification IEEE Std. 802.3 - 2000. 3 ports can be used as 100 Mbit/s MII interfaces, either Ports 0, 1 and 2 or Ports 0, 1 and 3. Note: Port 2 and Port 3 can not be used to receive data simultaneously, they are mutually exclusive. They may both be used for packet transmission if required. All Packet Interface signals are 5 V tolerant, and all outputs are high impedance while System Reset is LOW.
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Zarlink Semiconductor Inc.
ZL50130
Data Sheet
Signal M_MDC
I/O O H23
Package Balls
Description MII management data clock. Common for all four MII ports. It has a minimum period of 400 ns (maximum freq. 2.5 MHz), and is independent of the TXCLK and RXCLK. MII management data I/O. Common for all four MII ports at up to 2.5 MHz. It is bi-directional between the ZL50130 and the Ethernet station management entity. Data is passed synchronously with respect to M_MDC.
M_MDIO
ID/ OT
G26
Table 2 - MII Management Interface Package Ball Definition
MII Port 0 Signal M0_LINKUP_LED I/O O AB23 Package Balls Description LED drive for MAC 0 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 0 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off NOTE: In MII mode this pin must be driven with the same clock as M0_RXCLK. MII - M0_RXCLK. Accepts the following frequencies: 25.0 MHz MII 100 Mbit/s MII - M0_COL. Collision Detection. This signal is independent of M0_TXCLK and M0_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation.
M0_ACTIVE_LED
O
AC26
M0_REFCLK
ID
AA24
M0_RXCLK
IU
AB22
M0_COL
ID
Y25
Table 3 - MII Port 0 Interface Package Ball Definition
23
Zarlink Semiconductor Inc.
ZL50130
MII Port 0 Signal M0_RXD[3:0] I/O IU [3] [2] [1] [0] V25 W26 U22 Y26 AA26 Package Balls
Data Sheet
Description Receive Data. Clocked on rising edge of M0_RXCLK.
M0_RXDV
ID
MII - M0_RXDV Receive Data Valid. Active high. This signal is clocked on the rising edge of M0_RXCLK. It is asserted when valid data is on the M0_RXD bus. MII - M0_RXER Receive Error. Active high signal indicating an error has been detected. Normally valid when M0_RXDV is asserted. Can be used in conjunction with M0_RXD when M0_RXDV signal is de-asserted to indicate a False Carrier. MII - M0_CRS Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high. MII Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbit/s AA23 W21 Y22 AA22 Transmit Data. Clocked on rising edge of M0_TXCLK (MII).
M0_RXER
ID
V26
M0_CRS
ID
U25
M0_TXCLK
IU
U24
M0_TXD[3:0]
O
[3] [2] [1] [0] V23
M0_TXEN
O
MII - M0_TXEN Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M0_TXCLK with the first preamble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high.
Table 3 - MII Port 0 Interface Package Ball Definition
24
Zarlink Semiconductor Inc.
ZL50130
MII Port 0 Signal M0_TXER I/O O V22 Package Balls
Data Sheet
Description MII - M0_TXER Transmit Error. Transmitted synchronously with respect to M0_TXCLK, and active high. When asserted (with M0_TXEN also asserted) the ZL50130 will transmit a non-valid symbol, somewhere in the transmitted frame.
Table 3 - MII Port 0 Interface Package Ball Definition
MII Port 1 Signal M1_LINKUP_LED I/O O F26 Package Balls Description LED drive for MAC 1 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 1 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off NOTE: In MII mode this pin must be driven with the same clock as M1_RXCLK. MII - M1_RXCLK. Accepts the following frequencies: 25.0 MHz MII 100 Mbit/s MII - M1_COL. Collision Detection. This signal is independent of M1_TXCLK and M1_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation. N25 N24 R26 T26 Receive Data. Clocked on rising edge of M1_RXCLK (MII).
M1_ACTIVE_LED
O
AB25
M1_REFCLK
ID
M22
M1_RXCLK
IU
M23
M1_COL
ID
R25
M1_RXD[3:0]
IU
[3] [2] [1] [0]
Table 4 - MII Port 1 Interface Package Ball Definition
25
Zarlink Semiconductor Inc.
ZL50130
MII Port 1 Signal M1_RXDV I/O ID M26 Package Balls
Data Sheet
Description MII - M1_RXDV Receive Data Valid. Active high. This signal is clocked on the rising edge of M1_RXCLK. It is asserted when valid data is on the M1_RXD bus. MII - M1_RXER Receive Error. Active high signal indicating an error has been detected. Normally valid when M1_RXDV is asserted. Can be used in conjunction with M1_RXD when M1_RXDV signal is de-asserted to indicate a False Carrier. MII - M1_CRS Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high. MII Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbit/s
M1_RXER
ID
L21
M1_CRS
ID
L23
M1_TXCLK
IU
L22
M1_TXD[3:0]
O
[3] [2] [1] [0] P23
R22 P21 T22 R21
Transmit Data. Clocked on rising edge of M1_TXCLK (MII).
M1_TXEN
O
MII - M1_TXEN Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M1_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high.
Table 4 - MII Port 1 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50130
MII Port 1 Signal M1_TXER I/O O N23 Package Balls
Data Sheet
Description MII - M1_TXER Transmit Error. Transmitted synchronously with respect to M1_TXCLK, and active high. When asserted (with M1_TXEN also asserted) the ZL50130 will transmit a non-valid symbol, somewhere in the transmitted frame.
Table 4 - MII Port 1 Interface Package Ball Definition
MII Port 2 Note: This port must not be used to receive data at the same time as port 3, they are mutually exclusive. Signal M2_LINKUP_LED I/O O G23 Package Balls Description LED drive for MAC 2 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 2 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off MII Receive Clock. Accepts the following frequencies: 25.0 MHz MII 100 Mbit/s Collision Detection. This signal is independent of M2_TXCLK and M2_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation. AD25 AC23 [1] [0] AB21 AD24 Receive Data. Clocked on rising edge of M2_RXCLK. Receive Data Valid. Active high. This signal is clocked on the rising edge of M2_RXCLK. It is asserted when valid data is on the M2_RXD bus.
M2_ACTIVE_LED
O
AB24
M2_RXCLK
IU
AA19
M2_COL
ID
AE26
M2_RXD[3:0] M2_RXDV
IU ID
[3] [2] AA20
Table 5 - MII Port 2 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50130
MII Port 2 Note: This port must not be used to receive data at the same time as port 3, they are mutually exclusive. Signal M2_RXER I/O ID AC24 Package Balls
Data Sheet
Description Receive Error. Active high signal indicating an error has been detected. Normally valid when M2_RXDV is asserted. Can be used in conjunction with M2_RXD when M2_RXDV signal is de-asserted to indicate a False Carrier. Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high. MII Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbit/s
M2_CRS
ID
AC25
M2_TXCLK
IU
AD26
M2_TXD[3:0] M2_TXEN
O O
[3] [2] AC22
AE25 AD23
[1] [0]
AC21 AE24
Transmit Data. Clocked on rising edge of M2_TXCLK Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M2_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high. Transmit Error. Transmitted synchronously with respect to M2_TXCLK, and active high. When asserted (with M2_TXEN also asserted) the ZL50130 will transmit a non-valid symbol, somewhere in the transmitted frame.
M2_TXER
O
AB20
Table 5 - MII Port 2 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
ZL50130
MII Port 3 Note: This port must not be used to receive data at the same time as port 2, they are mutually exclusive. Signal M3_LINKUP_LED I/O O G24 Package Balls
Data Sheet
Description LED drive for MAC 3 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off LED drive for MAC 3 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off MII Receive Clock. Accepts the following frequencies: 25.0 MHz MII 100 Mbit/s Collision Detection. This signal is independent of M3_TXCLK and M3_RXCLK, and is asserted when a collision is detected on an attempted transmission. It is active high, and only specified for half-duplex operation.
M3_ACTIVE_LED
O
AB26
M3_RXCLK
IU
K26
M3_COL
ID
J26
M3_RXD[3:0] M3_RXDV
IU ID
[3] [2] J21
J22 J23
[1] [0]
J24 J25
Receive Data. Clocked on rising edge of M3_RXCLK. Receive Data Valid. Active high. This signal is clocked on the rising edge of M3_RXCLK. It is asserted when valid data is on the M3_RXD bus. Receive Error. Active high signal indicating an error has been detected. Normally valid when M3_RXDV is asserted. Can be used in conjunction with M3_RXD when M3_RXDV signal is de-asserted to indicate a False Carrier. Carrier Sense. This asynchronous signal is asserted when either the transmission or reception device is non-idle. It is active high.
M3_RXER
ID
H26
M3_CRS
ID
H24
Table 6 - MII Port 3 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
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MII Port 3 Note: This port must not be used to receive data at the same time as port 2, they are mutually exclusive. Signal M3_TXCLK I/O IU H25 Package Balls
Data Sheet
Description MII only - Transmit Clock Accepts the following frequencies: 25.0 MHz MII 100 Mbit/s
M3_TXD[3:0] M3_TXEN
O O
[3] [2] K24
K23 L26
[1] [0]
L25 L24
Transmit Data. Clocked on rising edge of M3_TXCLK Transmit Enable. Asserted when the MAC has data to transmit, synchronously to M3_TXCLK with the first pre-amble of the packet to be sent. Remains asserted until the end of the packet transmission. Active high. Transmit Error. Transmitted synchronously with respect to M3_TXCLK, and active high. When asserted (with M3_TXEN also asserted) the ZL50130 will transmit a non-valid symbol, somewhere in the transmitted frame.
M3_TXER
O
K25
Table 6 - MII Port 3 Interface Package Ball Definition
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Zarlink Semiconductor Inc.
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4.2 External Memory Interface
Data Sheet
All External Memory Interface signals are 5 V tolerant. All External Memory Interface outputs are high impedance while System Reset is LOW. If the External Memory Interface is unused, all input pins may be left unconnected. Active low signals are designated by a # suffix, in accordance with the convention used in common memory data sheets. Signal RAM_DATA[63:0] I/O IU/ OT [63] [62] [61] [60] [59] [58] [57] [56] [55] [54] [53] [52] [51] [50] [49] [48] [47] [46] [45] [44] [43] [42] [41] [40] [39] [38] [37] [36] [35 [34] [33] [32] [7] [6] [5] [4] AD7 AE6 AF5 AB8 AC7 AD6 AE5 AF4 AF3 AE4 AD5 AA8 AB7 AF2 AC6 AE3 AD4 AC5 AA7 AB6 AB5 AC4 AD3 AE2 AA5 AB4 AC3 AD2 AE1 AD1 W6 Y5 L1 L2 L3 L4 Package Balls [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] [3] [2] [1] [0] K3 K4 J1 J2 J3 J4 H1 H2 H3 J5 G1 J6 H4 G2 H5 G3 F1 G4 F2 F3 G5 E1 E2 G6 F5 F4 E3 E4 D1 E5 D2 D4 L5 L6 K1 K2 Description Buffer memory data. Synchronous to rising edge of SYSTEM_CLK.
RAM_PARITY[7:0]
IU/ OT
Buffer memory parity. Synchronous to rising edge of SYSTEM_CLK. Bit [7] is parity for data byte [63:56], bit [0] is parity for data byte [7:0].
Table 7 - External Memory Interface Package Ball Definition
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Zarlink Semiconductor Inc.
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Signal RAM_ADDR[19:0] I/O O [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] U2 R4 T2 T1 P5 R3 R2 P4 R1 P3 P2 Package Balls [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] P1 N4 N3 N2 M1 M2 M4 M3 M6 M5
Data Sheet
Description Buffer memory address output. Synchronous to rising edge of SYSTEM_CLK.
RAM_BW_A#
O
Synchronous Byte Write Enable A (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[7:0]. Synchronous Byte Write Enable B (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[15:8]. Synchronous Byte Write Enable C (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[23:16]. Synchronous Byte Write Enable D (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[31:24]. Synchronous Byte Write Enable E (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[39:32]. Synchronous Byte Write Enable F (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[47:40]. Synchronous Byte Write Enable G (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[55:48]
RAM_BW_B#
O
T3
RAM_BW_C#
O
U3
RAM_BW_D#
O
V2
RAM_BW_E#
O
W1
RAM_BW_F#
O
V3
RAM_BW_G#
O
W2
Table 7 - External Memory Interface Package Ball Definition
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Signal RAM_BW_H# I/O O Y1 Package Balls
Data Sheet
Description Synchronous Byte Write Enable H (Active Low). Must be asserted same clock cycle as RAM_ADDR. Enables RAM_DATA[63:56]. Read/Write Enable output Read = high Write = low
RAM_RW#
O
U4
Table 7 - External Memory Interface Package Ball Definition
4.3
CPU Interface
All CPU Interface signals are 5 V tolerant. All CPU Interface outputs are high impedance while System Reset is LOW. Signal CPU_DATA[31:0] I/O I/ OT [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] AF25 AB19 AD22 AE23 AC20 AF24 AE22 AD21 AA17 AB18 AC19 AD20 AF23 AE21 AF22 AC18 AB13 AC13 AD13 AE13 AF12 AE12 AD12 AC12 AF11 AB12 AE11 AA12 Package Balls [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] AA16 AD19 AE20 AB17 AF21 AC17 AE19 AA15 AB16 AD18 AF19 AE18 AD17 AF20 AB15 AF18 AD11 AF10 AC11 AE10 AD10 AB11 AF9 AC10 AE9 AA11 Description CPU Data Bus. Bi-directional data bus, synchronously transmitted with CPU_CLK rising edge. NOTE: as with all ports in the ZL50130 device, CPU_DATA[0] is the least significant bit (lsb).
CPU_ADDR[23:2]
I
CPU Address Bus. Address input from processor to ZL50130, synchronously transmitted with CPU_CLK rising edge. NOTE: as with all ports in the ZL50130 device, CPU_ADDR[2] is the least significant bit (lsb).
Table 8 - CPU Interface Package Ball Definition
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Zarlink Semiconductor Inc.
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Signal CPU_CS I/O IU AF14 Package Balls
Data Sheet
Description CPU Chip Select. Synchronous to rising edge of CPU_CLK and active low. Is asserted with CPU_TS_ALE. Must be asserted with CPU_OE to asynchronously enable the CPU_DATA output during a read, including DMA read. CPU Write Enable. Synchronously asserted with respect to CPU_CLK rising edge, and active low. Used for CPU writes from the processor to registers within the ZL50130. Asserted one clock cycle after CPU_TS_ALE CPU Output Enable. Synchronously asserted with respect to CPU_CLK rising edge, and active low. Used for CPU reads from the processor to registers within the ZL50130. Asserted one clock cycle after CPU_TS_ALE. Must be asserted with CPU_CS to asynchronously enable the CPU_DATA output during a read, including DMA read. Synchronous input with rising edge of CPU_CLK. Latch Enable (ALE), active high signal. Asserted with CPU_CS, for a single clock cycle. CPU/DMA 1 Acknowledge Input. Active low synchronous to CPU_CLK rising edge. Used to acknowledge request from ZL50130 for a DMA write transaction. Only used for DMA transfers, not for normal register access. CPU/DMA 2 Acknowledge Input Active low synchronous to CPU_CLK rising edge. Used to acknowledge request from ZL50130 for a DMA read transaction. Only used for DMA transfers, not for normal register access.
CPU_WE
I
AD14
CPU_OE
I
AE14
CPU_TS_ALE
I
AE15
CPU_SDACK1
I
AF15
CPU_SDACK2
I
AD15
Table 8 - CPU Interface Package Ball Definition
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Zarlink Semiconductor Inc.
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Signal CPU_CLK I/O I AC14 Package Balls
Data Sheet
Description CPU PowerQUICCTM II Bus Interface clock input. 66 MHz clock, with minimum of 6ns high/low time. Used to time all host interface signals into and out of ZL50130 device. CPU Transfer Acknowledge. Driven from tri-state condition on the negative clock edge of CPU_CLK following the assertion of CPU_CS. Active low, asserted from the rising edge of CPU_CLK. For a read, asserted when valid data is available at CPU_DATA. The data is then read by the host on the following rising edge of CPU_CLK. For a write, is asserted when the ZL50130 is ready to accept data from the host. The data is written on the rising edge of CPU_CLK following the assertion. Returns to tri-state from the negative clock edge of CPU_CLK following the de-assertion of CPU_CS. CPU DMA 0 Request Output Active low synchronous to CPU_CLK rising edge. Asserted by ZL50130 to request the host initiates a DMA write. Only used for DMA transfers, not for normal register access. CPU DMA 1 Request Active low synchronous to CPU_CLK rising edge. Asserted by ZL50130 to indicate packet data is ready for transmission to the CPU, and request the host initiates a DMA read. Only used for DMA transfers, not for normal register access. CPU Interrupt 0 Request (Active Low) CPU Interrupt 1 Request (Active Low)
CPU_TA
OT
AB14
CPU_DREQ0
OT
AC15
CPU_DREQ1
OT
AE16
CPU_IREQO CPU_IREQ1
O O
AF17 AD16
Table 8 - CPU Interface Package Ball Definition
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Zarlink Semiconductor Inc.
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4.4 System Function Interface
Data Sheet
All System Function Interface signals are 5 V tolerant. The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to allow the PLL's to lock. Signal SYSTEM_CLK I/O I U6 Package Balls Description System Clock Input. The system clock frequency is 100 MHz. The frequency must be accurate to within 32 ppm in synchronous mode. System Reset Input. Active low. The system reset is asynchronous, and causes all registers within the ZL50130 to be reset to their default state. System Debug Enable. This is an asynchronous signal that, when de-asserted, prevents the software assertion of the debug-freeze command, regardless of the internal state of registers, or any error conditions. Active high.
SYSTEM_RST
I
V4
SYSTEM_DEBUG
I
U5
Table 9 - System Function Interface Package Ball Definition
4.5 4.5.1
Test Facilities Administration and Control Interface
All Administration and Control Interface signals are 5 V tolerant. Signal GPIO[15:0] I/O ID/ OT [15] [14] [13] [12] [11] [10] [9] [8] [2] [1] [0] AA4 AB3 AC2 AC1 AB2 Y4 W5 AA3 AF6 AB9 AC8 Package Balls [7] [6] [5] [4] [3] [2] [1] [0] AA2 Y3 AB1 Y2 W4 V5 AA1 W3 Description General Purpose I/O pins. Connected to an internal register, so customer can set user-defined parameters. Bits [4:0] reserved at startup or reset for memory TDL setup. See the ZL50130 Programmers Model for more details. Test Mode input - ensure these pins are tied to ground for normal operation. 000 SYS_NORMAL_MODE 001-010 RESERVED 011 SYS_TRISTATE_MODE 100-111 RESERVED
TEST_MODE[2:0]
ID
Table 10 - Administration/Control Interface Package Ball Definition
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Zarlink Semiconductor Inc.
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4.5.2 JTAG Interface
Data Sheet
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001). Signal JTAG_TRST I/O IU AE7 Package Balls Description JTAG Reset. Asynchronous reset. In normal operation this pin should be pulled low. JTAG Clock - maximum frequency is 25 MHz, typically run at 10 MHz. In normal operation this pin should be pulled either high or low. JTAG test mode select. Synchronous to JTAG_TCK rising edge. Used by the Test Access Port controller to set certain test modes. JTAG test data input. Synchronous to JTAG_TCK. JTAG test data output. Synchronous to JTAG_TCK.
JTAG_TCK
I
AD8
JTAG_TMS
IU
AA10
JTAG_TDI JTAG_TDO
IU O
AF7 AC9
Table 11 - JTAG Interface Package Ball Definition
4.6
Miscellaneous Inputs
Signal Package Balls AD9, AF8, R5, T4, AE8 AF16 Description Internally Connected. Tie to GND. Internally Connected. Tie to VDD_IO.
IC_GND IC_VDD_IO
Table 12 - Miscellaneous Inputs Package Ball Definitions
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Zarlink Semiconductor Inc.
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4.7 Power and Ground Connections
Signal VDD_IO J9 J13 J17 L9 N9 R9 U9 V11 V15 A1 F6 L11 L15 M13 N1 N13 N22 P12 P16 R13 T5 T14 AA6 AF13 F7 F20 K6 N6 Y6 AA13 T6 Package Balls J10 J14 J18 L18 N18 R18 U18 V12 V16 A13 F21 L12 L16 M14 N5 N14 N26 P13 P24 R14 T11 T15 AA21 AF26 F12 H6 K21 T21 Y21 AA14 J11 J15 K9 M9 P9 T9 V9 V13 V17 A26 K5 L13 M11 M15 N11 N15 P6 P14 R11 R15 T12 T16 AB10 F15 H21 M21 V6 AA9 AA18 J12 J16 K18 M18 P18 T18 V10 V14 V18 E22 K22 L14 M12 M16 N12 N16 P11 P15 R12 R16 T13 T24 AF1 Description
Data Sheet
3.3 V VDD Power Supply for IO Ring
GND
0 V Ground Supply
VDD_CORE
1.8 V VDD Power Supply for Core Region
A1VDD
1.8 V PLL Power Supply Table 13 - Power and Ground Package Ball Definition
4.8
Internal Connections
Signal Package Balls R6, AC16, AE17 Description Internally Connected. Must leave open circuit.
IC
Table 14 - No Connection Ball Definition
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Zarlink Semiconductor Inc.
ZL50130
5.0
5.1
Data Sheet
Miscellaneous
JTAG Interface and Board Level Test Features.
The JTAG interface is used to access the boundary scan logic for board level production testing.
5.2
* * *
External Component Requirements
Direct connection to PowerQUICCTM II (MPC8260) host processor and associated memory, but can support other processors with appropriate glue logic. Ethernet PHY for each MAC port Optional ZBT-SRAM for extended packet memory buffer depth
5.3
* * * * * *
Miscellaneous Features
System clock speed of 100 MHz Host clock speed of up to 66 MHz Debug option to freeze all internal state machines JTAG (IEEE1149) Test Access Port 3.3 V I/O Supply rail with 5 V tolerance 1.8 V Core Supply rail
6.0
Memory Map and Register Definitions
All memory map and register definitions are included in the ZL50130 Programmers Model document.
7.0
7.1
Test Modes Operation
Overview
The ZL50130 supports the following modes of operation.
7.1.1
System Normal Mode
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access Port and Boundary Scan Architecture. Each variant has it's own dedicated .bsdl file which fully describes it's boundary scan architecture.
7.1.2
System Tri-State Mode
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the development board.
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Zarlink Semiconductor Inc.
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7.2 Test Mode Control
Data Sheet
The System Test Mode is selected using the dedicated device input bus test_mode[2:0] as follows in Table 15. System Test Mode SYS_NORMAL_MODE SYS_TRI_STATE_MODE test_mode[2:0] 3'b000 3'b011
Table 15 - Test Mode Control
7.3
System Normal Mode
Selected by test_mode[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins may be configured by the ADM module as either inputs or outputs.
7.4
System Tri-state Mode
Selected by test_mode[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
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Zarlink Semiconductor Inc.
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8.0
8.1
Data Sheet
DC Characteristics
Absolute Maximum Ratings*
Parameter Symbol VDD_IO VDD_CORE VDD_PLL VI VI_5V IIN IO PD TS Min. -0.5 -0.5 -0.5 -0.5 -0.5 -55 Max. 5.0 2.5 2.5 VDD + 0.5 7.0 10 15 4 +125 Units V V V V V mA mA W C
I/O Supply Voltage Core Supply Voltage PLL Supply Voltage Input Voltage Input Voltage (5 V tolerant inputs) Continuous current at digital inputs Continuous current at digital outputs Package power dissipation Storage Temperature
*Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage measurements are with respect to ground (VSS) unless otherwise stated. *The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply current is available. To be safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.
8.2
Recommended Operating Conditions
Characteristics Symbol TOP TJ VDD_IO VDD_CORE VDD_PLL VIL VIH VIH_5V Min. -40 -40 3.0 1.65 1.65 2.0 2.0 Typ. 25 3.3 1.8 1.8 Max. +85 125 3.6 1.95 1.95 0.8 VDD_IO 5.5 Units C C V V V V V V Test Condition
Operating Temperature Junction temperature Positive Supply Voltage, I/O Positive Supply Voltage, Core Positive Supply Voltage, Core Input Voltage Low - all inputs Input Voltage High Input Voltage High, 5 V tolerant inputs
Typical figures are at 25C and are for design aid only, they are not guaranteed and not subject to production testing. Voltage measurements are with respect to ground (VSS) unless otherwise stated
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Zarlink Semiconductor Inc.
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8.3 DC Characteristics
Characteristics Input Leakage Output (High impedance) Leakage Input Capacitance Output Capacitance Pullup Current Pullup Current, 5 V tolerant inputs Pulldown Current Pulldown Current, 5 V tolerant inputs Core 1.8 V supply current PLL 1.8 V supply current Symbol ILEIP ILEOP CIP COP IPU IPU_5V IPD IPD_5V IDD_CORE IDD_PLL 1 4 -27 -110 27 110 950 1.30 Min. Typ. Max. 1 2 Units. A A pF pF A A A A mA mA
Data Sheet
Test Condition No pull up/down VDD_IO = 3.6 V No pull up/down VDD_IO = 3.6 V
Input at 0 V Input at 0 V Input at VDD_IO Input at VDD_IO
I/O 3.3 V supply current IDD_IO 120 mA Typical characteristics are at 1.8 V core, 3.3 V I/O, 25C and typical processing. The min and max values are defined over all process conditions, from -40 to 125C junction temperature, core voltage 1.65 to 1.95 V and I/O voltage 3.0 and 3.6 V unless otherwise stated.
8.4
Input Levels
Characteristics Symbol VIL VIH VT+ VT2.0 1.6 1.2 Min. Typ. Max. 0.8 Units V V V V Test Condition
Input Low Voltage Input High Voltage Positive Schmitt Threshold Negative Schmitt Threshold
Table 16 - Input Levels
8.5
Output Levels
Characteristics Symbol VOL Min. Typ. Max. 0.4 Units V Test Condition IOL = 6 mA. IOL = 12 mA for packet interface (m*) pins and GPIO pins. IOL = 24 mA for LED pins. IOH = 6 mA. IOH = 12 mA for packet interface (m*) pins and GPIO pins. IOH = 24 mA for LED pins.
Output Low Voltage
Output High Voltage
VOH
2.4
V
Table 17 - Output Levels
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Zarlink Semiconductor Inc.
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9.0
9.1
Data Sheet
AC Characteristics
Packet Interface Timing
Data for the MII packet switching is based on Specification IEEE Std. 802.3 - 2000.
9.1.1
MII Transmit Timing
Parameter Symbol tCC tCHI tCLO tCR tCF tDV tEV tER 100 Mbit/s Min. 14 14 1 1 1 Typ. 40 Max. 26 26 5 5 25 25 25 Units ns ns ns ns ns ns ns ns Load = 25 pF Load = 25 pF Load = 25 pF Notes
TXCLK period TXCLK high time TXCLK low time TXCLK rise time TXCLK fall time TXCLK rise to TXD[3:0] active delay (TXCLK rising edge) TXCLK to TXEN active delay (TXCLK rising edge) TXCLK to TXER active delay (TXCLK rising edge)
Table 18 - MII Transmit Timing - 100 Mbit/s
tCC TXCLK tEV TXEN tDV TXD[3:0] tER TXER tER
tCL
tCH tEV
Figure 7 - MII Transmit Timing Diagram
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Zarlink Semiconductor Inc.
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9.1.2 MII Receive Timing
Parameter RXCLK period RXCLK high wide time RXCLK low wide time RXCLK rise time RXCLK fall time RXD[3:0] setup time (RXCLK rising edge) RXD[3:0] hold time (RXCLK rising edge) RXDV input setup time (RXCLK rising edge) RXDV input hold time (RXCLK rising edge) RXER input setup time (RXCL edge) RXER input hold time (RXCLK rising edge) Symbol tCC tCH tCL tCR tCF tDS tDH tDVS tDVH tERS tERH 100 Mbit/s Min. 14 14 10 5 10 5 10 5 Typ. 40 20 20 Max. 26 26 5 5 Units ns ns ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
Table 19 - MII Receive Timing - 100 Mbit/s
tCC RXCLK tDVS RXDV tDS RXD[3:0] tERS RXER tERH tDH
tCLO
tCHI tDVH
Figure 8 - MII Receive Timing Diagram
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Zarlink Semiconductor Inc.
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9.1.3 Management Interface Timing
Data Sheet
The management interface is common for all inputs and consists of a serial data I/O line and a clock line. Parameter M_MDC Clock Output period M_MDC high M_MDC low M_MDC rise time M_MDC fall time M_MDIO setup time (MDC rising edge) M_MDIO hold time (M_MDC rising edge) M_MDIO Output Delay (M_MDC rising edge) Symbol tMP tMHI tMLO tMR tMF tMS tMH tMD Min. 1990 900 900 10 10 1 Typ. 2000 1000 1000 Max. 2010 1100 1100 5 5 300 Units ns ns ns ns ns ns ns ns Note 1 Note 1 Note 2 Notes Note 1
Table 20 - MAC Management Timing Specification
Note 1: Note 2: Refer to Clause 22 in IEEE802.3 (2000) Standard for input/output signal timing characteristics Refer to Clause 22C.4 in IEEE802.3 (2000) Standard for output load description of MDIO
tMHI M_MDC tMS M_MDIO tMH
tMLO
Figure 9 - Management Interface Timing for Ethernet Port - Read
tMP M_MDC tMD M_MDIO
Figure 10 - Management Interface Timing for Ethernet Port - Write
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Zarlink Semiconductor Inc.
ZL50130
9.2 External Memory Interface Timing
Data Sheet
The timings for the External Memory Interface are based on the requirements of a ZBT-SRAM device, with the system clock speed at 100 MHz.
Parameter RAM_DATA[63:0] Output Valid Delay RAM_RW/RAM_ADDR[19:0] Delay RAM_BW[7:0]# Delay RAM_DATA[63:0] Setup Time RAM_DATA[63:0] Hold Time RAM_PARITY[7:0] Output Valid Delay RAM_PARITY[7:0] Setup Time RAM_PARITY[7:0] Hold Time
Symbol tRDV tRAV tRBW tRDS tRDH tRPV tRPS tRPS
Min. 2 0.5 2 0.5
Typ. -
Max. 4 4 4 4 -
Units ns ns ns ns ns ns ns ns
Notes Load CL = 30 pF Load CL = 30 pF Note 1 Load CL = 30 pF
Load CL = 30 pF
Table 21 - External Memory Timing
Note 1: Must be capable of driving TWO separate RAM loads simultaneously
n SCLK
Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
Phase 7
Phase 8
tRAV RAM_ADDR[19:0]
A1 - READ A2 - WRITE A3 - WRITE A4 - READ A5 - READ A6 - WRITE A7 - READ A8 - WRITE A1 A2 A3 A4 A5 A6
tRAV
A7 A8
tRAV RAM_RW tRBW RAM_BW[7:0]
BW1 BW2 BW3 BW4 BW5 BW6
tRAV
BW7
BW8
tRDH tRDS
D(A1)
tRDV
Q(A2)
tRDH tRDS
Q(A3) D(A4) D(A5)
tRDV
Q(A6)
RAM_DATA[63:0] tRPS RAM_PARITY[7:0]
tRPH
P(A1)
tRPV
P(A2) P(A3) P(A4) P(A5)
tRPV
P(A6)
Figure 11 - External RAM Read and Write timing
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Zarlink Semiconductor Inc.
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9.3 CPU Interface Timing
Parameter CPU_CLK Period CPU_CLK High Time CPU_CLK Low Time CPU_CLK Rise Time CPU_CLK Fall Time CPU_ADDR[23:2] Setup Time CPU_ADDR[23:2] Hold Time CPU_DATA[31:0] Setup Time CPU_DATA[31:0] Hold Time CPU_CS Setup Time CPU_CS Hold Time CPU_WE/CPU_OE Setup Time CPU_WE/CPU_OE Hold Time CPU_TS_ALE Setup Time CPU_TS_ALE Hold Time CPU_SDACK1/CPU_SDACK2 Setup Time CPU_SDACK1/CPU_SDACK2 Hold Time CPU_TA Output Valid Delay CPU_DREQ0/CPU_DREQ1 Output Valid Delay CPU_IREQ0/CPU_IREQ1 Output Valid Delay CPU_DATA[31:0] Output Valid Delay CPU_CS to Output Data Valid CPU_OE to Output Data Valid CPU_CLK(falling) to CPU_TA Valid Symbol tCC tCCH tCCL tCCR tCCF tCAS tCAH tCDS tCDH tCSS tCSH tCES tCEH tCTS tCTH tCKS tCKH tCTV tCWV tCRV tCDV tSDV tODV tOTV 4 2 4 2 4 2 5 2 4 2 2 2 2 2 2 2 3.2 3.3 11.3 6 6 7 10.4 10.4 9.5 6 6 4 4 Min. Typ. 15.152 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
Note 1 Note 1,2 Note 1 Note 1 Note 1
Table 22 - CPU Timing Specification
Note 1: Note 2: Load = 50 pF maximum The maximum value of tCTV may cause setup violations if directly connected to the MPC8260. See Section 11.2 for details of how to accommodate this during board design
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Zarlink Semiconductor Inc.
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Data Sheet
The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of CPU_TA, not at the positive clock edge during the assertion of CPU_TA.
tCC CPU_CLK tCAS CPU_ADDR[23:2] tCSS CPU_CS tCES CPU_OE CPU_WE tCTS CPU_TS_ALE tSDV CPU_DATA[31:0] tOTV CPU_TA NOTE: CPU_DATA is valid when CPU_TA is asserted. CPU_DATA will remain valid while both CPU_CS and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted. CPU_CS and CPU_OE must BOTH be asserted to enable the CPU_DATA output. tCTV tCTV tOTV tODV tCDV tODV tSDV tCTH tCEH tCSH tCAH 0 or more cycles
Figure 12 - CPU Read - MPC8260
tCC 0 or more cycles CPU_CLK tCAS CPU_ADDR[23:2] tCSS CPU_CS CPU_OE tCES CPU_WE tCTH tCTS CPU_TS_ALE tCDS CPU_DATA[31:0] tOTV CPU_TA tCTV tCTV tCDH tCEH tCAH
0 or more cycles
tCSH
tOTV
NOTE: Following assertion of CPU_TA, CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed.
Figure 13 - CPU Write - MPC8260
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Zarlink Semiconductor Inc.
ZL50130
tCC CPU_CLK tCWV CPU_DREQ1 tCKS CPU_SDACK2 tCSS CPU_CS tCES CPU_OE CPU_WE tCTH tCTS CPU_TS_ALE tSDV CPU_DATA[31:0] tOTV CPU_TA tCTV tCTV tODV tCDV tODV tSDV tCEH tCSH tCKH tCWV
Data Sheet
0 or more cycles
tOTV
NOTE: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid when CPU_TA is asserted (always timed as shown). CPU_DATA will remain valid while CPU_CS and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted. CPU_CS and CPU_OE must BOTH be asserted to enable
the CPU_DATA output.
Figure 14 - CPU DMA Read
CPU_CLK tCWV CPU_DREQ0
- MPC8260
tCC tCWV tCKS tCKH tCSH 0 or more cycles
CPU_SDACK1 tCSS CPU_CS CPU_OE tCES CPU_WE tCTS CPU_TS_ALE tCDS CPU_DATA[31:0] tOTV CPU_TA NOTE: CPU_SDACK1 must be asserted during the cycle shown. It may then be deasserted at any time. Following assertion of CPU_TA (always timed as shown), CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed. tCTV tCTV tOTV tCDH tCTH tCEH
Figure 15 - CPU DMA Write - MPC8260
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Zarlink Semiconductor Inc.
ZL50130
9.4 System Function Port
Parameter SYSTEM_CLK Frequency SYSTEM_CLK accuracy (synchronous master mode) SYSTEM_CLK accuracy (synchronous slave mode and asynchronous mode) Symbol CLKFR CLKACS CLKACA Min. Typ. 100 Max. 30 200 Units MHz ppm ppm
Data Sheet
Notes Note 1 and Note 2 Note 3 Note 4
Table 23 - System Clock Timing
Note 1: The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for a short duration while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the system clock (SYSTEM_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature coefficient of 0.1ppm/C, a 10C change in temperature while the DPLL is in will result in a frequency accuracy offset of 1ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift. The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e. frequency of clock output equals 8.192 MHz SYSTEM_CLK accuracy 0.005 ppm). The absolute SYSTEM_CLK accuracy must be controlled to 30 ppm in synchronous master mode to enable the internal DPLL to function correctly. In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may be relaxed slightly.
Note 2:
Note 3: Note 4:
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Zarlink Semiconductor Inc.
ZL50130
9.5 JTAG Interface Timing
Parameter JTAG_CLK period JTAG_CLK clock pulse width JTAG_CLK rise and fall time JTAG_TRST setup time Symbol tJCP tLOW, tHIGH tJRF tRSTSU Min. 40 20 0 10 Typ. 100 3 Max. Units ns ns ns ns
Data Sheet
Notes
With respect to JTAG_CLK falling edge. Note 1 Note 2 Note 2 Note 3 Note 3
JTAG_TRST assert time Input data setup time Input Data hold time JTAG_CLK to Output data valid JTAG_CLK to Output data high impedance JTAG_TMS, JTAG_TDI setup time JTAG_TMS, JTAG_TDI hold time JTAG_TDO delay JTAG_TDO delay to high impedance
tRST tJSU tJH tJDV tJZ tTPSU tTPH tTOPDV tTPZ
10 5 15 0 0 5 15 0 0
-
20 20 15 15
ns ns ns ns ns ns ns ns ns
Table 24 - JTAG Interface Timing
Note 1: Note 2: Note 3: JTAG_TRST is an asynchronous signal. The setup time is for test purposes only. Non Test (other than JTAG_TDI and JTAG_TMS) signal input timing with respect to JTAG_CLK Non Test (other than JTAG_TDO) signal output with respect to JTAG_CLK
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Zarlink Semiconductor Inc.
ZL50130
Data Sheet
tHIGH JTAG_TCK tTPH
tLOW
tJCP
tTPSU JTAG_TMS
tTPSU JTAG_TDI Don't Care tTOPDV JTAG_TDO HiZ
tTPH DC tTPZ HiZ
Figure 16 - JTAG Signal Timing
tLOW JTAG_TCK tRST JTAG_TRST
tHIGH
tRSTSU
Figure 17 - JTAG Clock and Reset Timing
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Zarlink Semiconductor Inc.
ZL50130
10.0
* * *
Data Sheet
Power Up sequence
To power up the ZL50130 the following procedure must be used: The Core supply must never exceed the I/O supply by more than 0.5 VDC. Both the Core supply and the I/O supply must be brought up together The System Reset and, if used, the JTAG Reset must remain low until at least 100 s after the 100 MHz system clock has stabilised. Note that if JTAG Reset is not used it must be tied low.
This is illustrated in the diagram shown in Figure 18.
I/O supply (3.3 V)
VDD
<0.5 VDC
Core supply (1.8 V)
t
RST
t
> 100s
SCLK
t
10ns
Figure 18 - Powering Up the ZL50130
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Zarlink Semiconductor Inc.
ZL50130
11.0 Design and Layout Guidelines
Data Sheet
This guide will provide information and guidance for PCB layouts when using the ZL50130. Specific areas of guidance are: * High Speed Clock and Data, Outputs and Inputs * CPU_TA Output
11.1
High Speed Clock & Data Interfaces
On the ZL50130 series of devices there are three high-speed data interfaces that need consideration when laying out a PCB to ensure correct termination of traces and the reduction of crosstalk noise. The interfaces being: * External Memory Interface * * MAC Interfaces CPU Interface
In general the output drivers used in the ZL50130 are capable of driving modest capacitive loads with a reasonably fast edge speed (<2.5 ns). Therefore these outputs are not designed to drive multiple loads, connectors, backplanes or cables. It is recommended that the outputs are suitably terminated using a series termination through a resistor as close to the output pin as possible. The purpose of the series termination resistor is to reduce reflections on the line. The value of the series termination and the length of trace the output can drive will depend on the driver output impedance, the characteristic impedance of the PCB trace (recommend 50 ohm), the distributed trace capacitance and the load capacitance. As a general rule of thumb, if the trace length is less than 1/6th of the equivalent length of the rise and fall times, then a series termination may not be required. the equivalent length of rise time = rise time (ps) / delay (ps/mm) For example: Typical FR4 board delay = 6.8 ps/mm Typical rise/fall time for a ZL50130 output = 2.5 ns critical track length = (1/6) x (2500/6.8) = 61 mm Therefore tracks longer than 61 mm will require termination. As a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is crosstalk. If the crosstalk is of sufficiently strong amplitude, false data can be induced in the trace and therefore it should be minimized in the layout. The voltage that the external fields cause is proportional to the strength of the field and the length of the trace exposed to the field. Therefore to minimize the effect of crosstalk some basic guidelines should be followed. First, increase separation of sensitive signals, a rough rule of thumb is that doubling the separation reduces the coupling by a factor of four. Alternatively, shield the victim traces from the aggressor by either routing on another layer separated by a power plane (in a correctly decoupled design the power planes have the same AC potential) or by placing guard traces between the signals usually held ground potential.
11.1.1
External Memory Interface - special considerations during layout
The timing of address, data and control are all related to the system clock which is also used by the external SSRAM to clock these signals. Therefore the propagation delay of the clock to the ZL50130 and the SSRAM must be matched to within 250 ps, worst case conditions. Trace lengths of theses signals must also be minimized (<100 mm) and matched to ensure correct operation under all conditions.
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Zarlink Semiconductor Inc.
ZL50130
11.1.2 MAC Interface - special considerations during layout
Data Sheet
The MII interface passes data to and from the ZL50130 with their related transmit and receive clocks. It is therefore recommended that the trace lengths for transmit related signals and their clock and the receive related signals and their clock are kept to the same length. By doing this the skew between individual signals and their related clock will be minimized.
11.1.3
Summary
Particular effort should be made to minimize crosstalk from ZL50130 outputs and ensuring fast rise time to these inputs. In Summary: * * * * Place series termination resistors as close to the pins as possible. minimize output capacitance. Keep common interface traces close to the same length to avoid skew. Protect input clocks and signals from crosstalk.
11.2
CPU TA Output
The CPU_TA output signal from the ZL50130 is a critical handshake signal to the CPU that ensures the correct completion of a bus transaction between the two devices. As the signal is critical, it is recommend that the circuit shown in Figure 19 is implemented in systems operating above 40 MHz bus frequency to ensure robust operation under all conditions. * The following external logic is required to implement the circuit: * * * * 74LCX74 dual D-type flip-flop (one section of two) 74LCX08 quad AND gate (one section of four) 74LCX125 quad tri-state buffer (one section of four) 4K7 resistor x2
+3V3
+3V3
R1 4K7 CPU_TA from ZL50130
R2 4K7 CPU_TA to CPU
D
Q
CPU_CLK to ZL50130
CPU_CS to ZL50130
Figure 19 - CPU_TA Board Circuit
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Zarlink Semiconductor Inc.
ZL50130
Data Sheet
The function of the circuit is to extend the TA signal, to ensure the CPU correctly registers it. Resistor R2 must be fitted to ensure correct operation of the TA input to the processor. It is recommended that the logic is fitted close to the ZL50130 and that the clock to the 74LCX74 is derived from the same clock source as that input to the ZL50130.
12.0
Physical Specification
The ZL50130 will be packaged in a PBGA device. Features: * Body Size: * * * * * Ball Count: Ball Pitch: Ball Matrix: Ball Diameter: Total Package Thickness: 35 mm x 35 mm (typ) 552 1.27 mm (typ) 26 x 26 0.75 mm (typ) 2.33 mm (typ)
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Zarlink Semiconductor Inc.
ZL50130
13.0
13.1
* * * * * * * * * * * * * *
Data Sheet
Reference Documents
External Standards/Specifications
IEEE Standard 1149.1-2001; Test Access Port and Boundary Scan Architecture IEEE Standard 802.3-2000; Local and Metropolitan Networks CSMA/CD Access Method and Physical Layer MPC8260AEC/D Revision 0.7; Motorola MPC8260 Family Hardware Specification RFC 768; UDP RFC 791; IPv4 RFC2460; IPv6 RFC 1889; RTP RFC 2661; L2TP RFC 1213; MIB II RFC 1757; Remote Network Monitoring MIB (for SMIv1) RFC 2819; Remote Network Monitoring MIB (for SMIv2) RFC 2863; Interfaces Group MIB IETF's PWE3 draft-ietf-l2tpext-l2tp-base-02 Optional Packet Memory Device - Micron MT55L128L32P1 8 Mb ZBT-SRAM
13.2
* * *
Zarlink ZL50130 Product Related Documentation
ZL50130 Programmers Model ZL50130 API Users Guide ZL50130 Product Preview
14.0
* * *
Related Products
24 Port 10/100 Mbit/s Ethernet Switch 4/8 Port Gigabit Ethernet Switch Ethernet Switches
MVTX260x MVTX280x ZL50418
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Zarlink Semiconductor Inc.
ZL50130
15.0
CPU DMA IETF IP JTAG L2TP LAN MAC MII MIB MPLS PLL PSN PWE3 SSRAM UDP VLAN WFQ ZBT
Data Sheet
Glossary
Central Processing Unit Direct Memory Access Internet Engineering Task Force Internet Protocol (version 4, RFC 791, version 6, RFC 2460) Joint Test Algorithms Group (generally used to refer to a standard way of providing a board-level test facility) Layer 2 Tunneling Protocol (RFC 2661) Local Area Network Media Access Control Media Independent Interface Management Information Base Multi Protocol Label Switching Phase Locked Loop Packet Switched Network Pseudo-Wire End-to-End Emulation (a working group of the IETF) Synchronous Static Random Access Memory User Datagram Protocol (RFC 768) Virtual Local Area Network Weighted Fair Queuing Zero Bus Turnaround, a type of synchronous SRAM
CONTEXT A programmed connection representing a unique packet stream.
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Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1 213837 12Dec02
2
19Aug03
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